As the transistor sizes are reducing in pursuit of Moore's law, increase in series resistance towards the channel is becoming a challenge. This is due to the fact that the performance of the device, such as for example, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and drain saturation current (IDsat) can adversely be influenced if the series resistance is not minimized. This has to do mainly with the increase in contact resistance, which is one of the main components of the series resistance.
Contact resistance is a function of the resistance of (1) contact metal fill, (2) interface metal/semiconductor resistivity and (3) contact area.
1. Resistance of the fill metal can depend on whether the material needs to be integrated with contact liners and what the contribution of these contact liners is to the overall resistance.
2. Metal/semiconductor resistivity can be a function of the number of active dopants at the interface and the choice of interface metal. In pursuit of Moore's Law, alternative material choices can be introduced instead of silicon, such as strained silicon (s-Si), strained germanium (s-Ge) SiGe, or III-V compound semiconductor materials, to form the channel of a field effect transistor (FET)
In this respect, the choice of interface metal may depend on the type of material in the source and drain (S/D) region of the FET, which is chosen among the aforementioned alternative materials to be integrated for nMOS and pMOS, respectively. Additionally, the formation and thermal stability of the electrical contact as a function of the choice of the interface metal can also play a role.
Additionally, with the device scaling in pursuit of Moore's Law, introduction of new FET designs such as fin-type FET (finFET) or Tri-gate FET has taken place. Thus, there is a trend to integrate taller fin structures at tighter pitch to maximize drive current per footprint (accelerated by fin depopulation considerations). This can lead to reduction in the contact area, which in turns can lead to an increase in contact resistance. Besides, in relation with the influence of contact area, contact opening can also be critical since the damage on the S/D region of the FET within the contact area is typically created during contact opening. Damage to the S/D region can risk altering the number of active dopants, which in turn can influence the aforementioned metal/semiconductor resistivity thus, and can result in an increase in contact resistance.
There is, therefore, a need for a method that can enable the formation of an electrical contact on or completely surrounding the source region and drain region of a FET without resulting in damage to the substrate in the source/drain region; thus can lead to an electrical contact having minimized contact resistance.